Very Large Scale Integration (VLSI) chips, such as network processors, may utilize a clock or clocks to operate the function or functions that the chip performs. The clock(s) may be generated from a phase lock loop (PLL) circuit or PLL circuits. During start-up or reset of the chip, there will be a period in which the PLL is attaining lock on a frequency (PLL lock period). In order to reduce contention and to initialize sequential elements during start-up, VLSI chips may utilize a slow speed bypass clock (provide to the chip by either a low speed ring oscillator or an externally generated clock) while external reset is asserted. After the de-assertion of reset, the PLL starts the process of locking to the specified frequency. While the PLL is in the process of attaining lock on the frequency, the clocks to the functional blocks may be disabled.
Once the PLL is locked, the clock or clocks can be generated from the PLL and applied to various functional blocks on the chip (the clocks to the functional blocks are enabled after the PLL has locked). Depending upon the frequency and the total capacitive load that the clock is driving, the sudden turn-on of the clocks after the PLL has locked may cause a large current rush (di/dt). A di/dt can result in localized and global voltage droops. The magnitude of this droop may depend on varying parameters including the power delivery, amount of on-die and off-chip de-coupling capacitance, and frequency response of the power supply. It is possible that the voltage droop caused by a large di/dt event may cause the PLL to lose lock, state elements on the chip to lose their reset value, or other errors or degradations of the chips performance.